1. Field of the Invention
This invention relates to a liquid crystal display and a method of fabricating the same, and more particularly, to a line on glass (LOG) liquid crystal display and a method of fabricating the same.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) controls a light transmittance of a liquid crystal having a dielectric anisotropy by applying an electric field to the liquid crystal, thereby displaying a picture. The LCD includes a liquid crystal display panel having liquid crystal cells arranged in matrix and a driving circuit for driving the liquid crystal display panel.
In the liquid crystal display panel, the liquid crystal cells arranged in matrix controls the light transmittance in accordance with the pixel signals to display a picture. The driving circuit includes a gate driver for driving gate lines of the liquid crystal display panel, a data driver for driving data lines, a timing controller for controlling a driving timing of the gate and the data drivers, and a power supply for supplying power signals to drive the liquid crystal display panel and the driving circuit.
The data driver and the gate driver are separated into a plurality of integrated circuits (ICs) and manufactured as a chip. Each of the integrated drive ICs is mounted in an opened IC area of a tape carrier package (TCP) or in a base film of the TCP by a chip on film (COF) system. Also, each of the integrated drive ICs is electrically connected to the liquid crystal display panel by a tape automated bonding (TAB) system. Alternatively, the drive IC may be directly mounted on the liquid crystal display panel by a chip on glass (COG) system. The timing controller and the power supply are manufactured into a chip shape to be mounted on a main printed circuit board (PCB).
The drive ICs connected to the liquid crystal display panel by the TCP uses a flexible printed circuit (FPC) and a sub-PCB to connect to the timing controller and the power supply on the main PCB. More specifically, the data drive ICs receive data control signals and pixel data from the timing controller, and power signals from the power supply mounted on the main PCB using the data FPC and the data PCB. Similarly, the gate drive ICs receive gate control signals from the timing controller, and power signal from the power supply mounted on the main PCB using the gate FPC and the gate PCB. The drive ICs mounted on the liquid crystal display panel by the COG system receive control signals and pixel signals from the timing controller, and power signals from the power supply mounted on the main PCB through the FPC and line on glass (LOG) signal lines provided at the liquid crystal display panel.
Recent improvements in the LCD technology include adapting the LOG signal lines to eliminate the PCB even when the drive ICs are connected to the LCD panel via the TCP. Specifically, the gate PCB delivering a relatively small number of signals is removed, thereby, reducing the thickness of the LCD. In addition, signal lines for applying the gate control signals and the power signals to the gate drive ICs are provided in a LOG liquid crystal display panel. Accordingly, the gate drive ICs mounted in the TCP receive the gate control signals from the timing controller and the power signals from the power supply using the main PCB, FPC, the data PCB, the data TCP, the LOG signal lines and the gate TCP. In this case, the gate control signals and the gate power signals applied to the gate drive ICs are distorted by line resistances of the LOG signal lines, thereby causing the deterioration of quality in pictures displayed on the liquid crystal display panel.
More specifically, as shown in FIG. 1, a related art LOG LCD, which is separated from the gate PCB, includes a main PCB 20 provided with a timing controller 22 and a power supply 24, a data PCB 16 connected to the main PCB 20 via a FPC 18, a data TCP 12 having a data driving IC 14 and being connected between the data PCB 16 and a liquid crystal display panel 6, and a gate TCP 8 having a gate driving IC 10 and being connected to the liquid crystal display panel 6.
In the liquid crystal display panel 6, a thin film transistor array substrate 2 and a color filter array substrate 4 are joined to each other with a liquid crystal interposed therebetween. Such a liquid crystal display panel 6 is provided with liquid crystal cells, in which each liquid crystal cell is driven independently by a thin film transistor (TFT) provided at the intersections of gate lines GL and data lines DL. The thin film transistor applies a pixel signal from the data line DL to the liquid crystal cell in response to a scanning signal from the gate line GL.
The data drive ICs 14 are connected to the data lines DL, via the data TCP 12 and a data pad of the liquid crystal display panel 6. The data drive ICs 14 convert a pixel data into an analog pixel signal and apply to the data lines DL. The data drive ICs 14 receive a data control signal, a pixel data, and power signals from the timing controller 22 and the power supply 24 mounted on the main PCB 20 using the data PCB 16 and the FPC 18.
The gate drive ICs 10 are connected to the gate lines GL via the gate TCP 8 and a gate pad of the liquid crystal display panel 6. The gate drive ICs 10 sequentially apply a scanning signal having a high gate voltage VGH to the gate lines GL. Furthermore, the gate drive ICs 10 apply a low gate voltage VGL to the gate lines GL in the remaining interval when the high gate voltage VGH is not supplied.
The gate control signals from the timing controller 22 and the power signals from the power supply 24 are applied to the data TCP 12 via the FPC 18 and the data PCB 16. The grate control signals and the power signals applied through the data TCP 12 are supplied to the gate TCP 8, via a LOG signal line group 26 provided at the edge portion of the thin film transistor array substrate 2. The gate control signals and the power signals applied to the gate TCP 8 are input within the gate drive IC 10 via input terminals of the gate drive IC 10. Furthermore, the gate control signals and the power signals are output via output terminals of the gate drive IC 10, and applied to the next gate drive IC 10 mounted in the next gate TCP 8 via the gate TCP 8 and the LOG signal line group 26.
The LOG signal line group 26 typically comprises signal lines for supplying direct current driving voltages from the power supply 24 (for example, a low gate voltage VGL, a high gate voltage VGH, a common voltage VCOM, a ground voltage GND and a base driving voltage VCC), and gate control signals from the timing controller 22 (for example, a gate start pulse GSP, a gate shift clock signal GSC and a gate enable signal GOE).
The LOG signal line group 26 as described is formed in a fine pattern from the same gate metal layer as the gate lines at a specific pad area of the thin film transistor array substrate 2. Furthermore, the LOG signal line group 26 is in contact with the gate TCP 8 by ACF bonding, thereby increasing an area of contact with the gate TCP 8 to enlarge a contact resistance. Thus, the LOG signal line group 26 has a larger line resistance than the signal lines on the existent gate PCB. This line resistance distorts gate control signals (i.e., GSP, GSC and GOE) and power signals (i.e., VGH, VGL, VCC, GND and VCOM) transmitted via the LOG signal line group 26, thereby generating errors, such as horizontal stripe, a stain, a cross talk in a dot pattern and a greenish color to cause deterioration in picture quality.
For instance, as shown in FIG. 2, the related art LOG signal line group 26 supplying the gate control signals (i.e., GSP, GSC and GOE) and the power signals (i.e., VGH, VGL, VCC, GND and VCOM) is comprises first to third LOG signal line groups LOG1 to LOG3 between the gate TCPs 8. The groups LOG1 to LOG3 have line resistances LΩ, MΩ and NΩ proportional to the line length, respectively. The groups LOG1 to LOG3 are connected to each other in series via the gate TCP 8 and the gate drive IC 10. Such LOG signal line groups LOG1 to LOG3 generate a level difference between the gate control signals (i.e., GSP, GSC and GOE) and the power signals (i.e., VGH, VGL, VCC, GND and VCOM) input for each of the corresponding gate drive IC 10. As a result, a difference in brightness is generated among horizontal line blocks A to C driven by different gate drive IC 10 to cause a horizontal line stripe 32.
More specifically, the first gate drive IC 10 is supplied with the gate control signals GSP, GSC and GOE and the power signals VGH, VGL, VCC, GND and VCOM voltage-dropped by the line resistance LΩ of the first LOG signal line group LOG1. The second gate drive IC 10 is supplied with those voltage-dropped by the line resistances LΩ+MΩ of the first and second LOG signal line groups LOG1 and LOG2. The third gate drive IC 10 is supplied with those voltage-dropped by the line resistances LΩ+MΩ+NΩ of the first to third LOG signal line groups LOG1 to LOG3. Thus, a voltage difference is generated among gate signals VG1 to VG3 applied to the gate lines at the first to third horizontal blocks A to C, thereby causing horizontal line stripes 32 among the horizontal line blocks A to C.
Difference in the gate voltage by the gate drive IC 10 unit can be compensated by increasing a sectional area of the LOG signal line group 26 in inverse proportion to the line length. However, since the edge portion of the liquid crystal display panel 6 provided with the LOG signal line group 26 is limited, there is a limitation to increase a sectional area.